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| HM6289 Series 16384-word x 4-bit High Speed CMOS Static RAM (with OE) Description The Hitachi HM6289 is a high speed 64 k static RAM organized as 16-kword x 4-bit. It realizes high speed access time (25/35 ns) and low power consumption, employing CMOS process technology. It is most advantageous for high speed and high density memory, such as in cache memory for mainframes or 32-bit MPUs. The HM6289, packaged in a 300-mil SOJ, is available for high density mounting. The low power version retains the data with battery backup. Features * High speed access time: tAA : 25/35 ns (max) tOE: 12/15 ns (max) * High density 24-pin S0J package * Low power Active mode: 300 mW (typ) Standby mode: 100 W (typ) * Single 5 V supply * Completely static memory: No clock or timing strobe required * Equal access and cycle times * Directly TTL compatible: All inputs and outputs Ordering Information Type No. HM6289JP-25 HM6289JP-35 HM6289LJP-25 HM6289LJP-35 Access Time 25 ns 35 ns 25 ns 35 ns Package 300-mill, 24-pin SOJ (CP-24D) HM6289 Series Pin Arrangement A0 A1 A2 A3 A4 A5 A6 A7 A8 CS OE VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A13 A12 A11 A10 A9 NC I/O1 I/O2 I/O3 I/O4 WE (Top view) Pin Description Pin Name A0 - A13 I/O1 - I/O4 CS OE WE VCC VSS Function Address Input/output Chip select Output enable Write enable Power supply Ground 2 HM6289 Series Block Diagram A0 A1 A2 A3 A4 A5 A6 I/O1 I/O2 I/O3 I/O4 A7 A8 A9 A10A11A12A13 Input Data Control VCC VSS Row Decoder Memory Matrix 128 x 512 Column I/O Column Decoder CS WE OE Truth Table CS H L L L OE x L H L WE x H L L Mode Not selected Read Write Write VCC current I SB , I SB1 I CC I CC I CC I/O pin High-Z Dout Din Din Ref. cycle -- Read cycle (1) - (3) Write cycle (1) - (2) Write cycle (3) - (6) Note: x: Don't care (H or L). 3 HM6289 Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Power dissipation Operating temperature range Storage temperature range Storage temperature range under bias Note: Symbol Vin PT Topr Tstg Tbias Value -0.5 1.0 0 to +70 -55 to +125 -10 to +85 *1 Unit to +7.0 V W C C C 1. Vin min = -2.0 V for pulse width 10 ns. Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VCC VSS Input high (logic 1) voltage Input low (logic 0) voltage Note: VIH VIL Min 4.5 0 2.2 -0.5 *1 Typ 5.0 0 -- -- Max 5.5 0 6.0 0.8 Unit V V V V 1. VIL min = -2.0 V for pulse widths 10 ns. DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) Parameter Input leakage current Output leakage current Operating VCC current Standby V CC current Standby V CC current (1) Symbol |ILI| |ILO | I CC I SB I SB1 Min -- -- -- -- -- Typ*1 -- -- 60 15 0.02 Max 2.0 2.0 120 30 2.0 Unit A A mA mA mA Test Conditions VCC = Max Vin = 0 V to VCC CS = VIH, VI/O = 0 V to VCC CS = VIL, Iout = 0 mA, min cycle CS = VIH, min cycle CS V CC - 0.2 V, 0 V Vin 0.2 V or V CC - 0.2 V Vin I SB1*2 Output low voltage Output high voltage VOL VOH -- -- 2.4 -- -- -- 0.1 0.4 -- A V V I OL = 8 mA I OH = -4.0 mA Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. L-version 4 HM6289 Series Capacitance (Ta = 25C, f = 1 MHz)*1 Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min -- -- Typ -- -- Max 6 8 Unit pF pF Test Conditions Vin = 0 V VI/O = 0 V 1. These parameters are sampled and not 100% tested. AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted) Test Conditions * * * * Input pulse levels: V SS to 3.0 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: See figures +5 V 480 Dout 255 Dout 255 +5 V 480 30 pF*1 5 pF*1 Output load (A) Output load (B) (for tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, and tOW ) Note: 1. Including scope and jig. 5 HM6289 Series Read Cycle HM6289-25 Parameter Read cycle time Address access time Chip select access time Chip selection to output in low-Z Output enable to output valid Output enable to output in low-Z Chip deselection to output in high-Z Chip disable to output high-Z Output hold from address change Note: Symbol t RC t AA t ACS t CLZ t OE t OLZ t CHZ t OHZ t OH *1 *1 *1 *1 HM6289-35 Min 35 -- -- 5 -- 0 0 0 5 Max -- 35 35 -- 15 -- 20 10 -- Unit ns ns ns ns ns ns ns ns ns Min 25 -- -- 5 -- 0 0 0 3 Max -- 25 25 -- 12 -- 12 10 -- 1. Output transition is measured 200 mV from steady state voltage with load (B). These parameters are sampled and not 100% tested. 6 HM6289 Series Read Timing Waveform (1) tRC Address tAA OE tOE tOLZ CS tACS tCLZ Dout High impedance Valid Data tOHZ tCHZ tOH Note: WE is high for read cycle. Read Timing Waveform (2) tRC Address tAA tOH Dout Valid Data tOH Notes: 1. WE is high for read cycle. 2. Device is continously selected, CS = VIL. 3. OE = VIL 7 HM6289 Series Read Timing Waveform (3) CS tACS tCLZ Dout High impedance Valid Data tCHZ Notes: 1. WE is high for read cycle. 2. Address valid prior to or coincident with CS transition low. 3. OE = VIL Write Cycle HM6289-25 Parameter Write cycle time Chip selection to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Output disable to output in high-Z Write to output in high-Z *1 *1 HM6289-35 Max -- -- -- -- -- -- 10 8 -- -- -- Min 35 30 30 0 30 0 0 0 20 0 5 Max -- -- -- -- -- -- 10 10 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns Symbol t WC t CW t AW t AS t WP t WR t OHZ t WHZ t DW t DH *1 Min 25 20 20 0 20 0 0 0 12 0 5 Data to write time overlap Data hold from write time Output active from end of write Note: t OW 1. Output transition is measured 200 mV from steady state voltage with load (B). These parameters are sampled and not 100% tested. 8 HM6289 Series Write Timing Waveform (1) (OE = High, WE = Controlled) tWC Address tCW CS tAW tAS WE tDW Din High impedance Dout Note: 1. A write occurs during the overlap of a low CS and a low WE (tWP). Valid Data tDH tWP *1 tWR 9 HM6289 Series Write Timing Waveform (2) (OE = High, CS = Controlled) tWC Address tAS CS tAW tWP *1 WE tDW Din High impedance Dout Note: 1. A write occurs during the overlap of a low CS and a low WE (tWP). Valid Data tDH tWR tCW 10 HM6289 Series Write Timing Waveform (3) (OE = Clocked, WE = Controlled) tWC Address OE tCW CS tAW tAS WE tOHZ *2 Dout Din High impedance tDW Valid Data tDH tWP *1 tWR tOLZ *2 Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of write cycle. 11 HM6289 Series Write Timing Waveform (4) (OE = Clocked, CS = Controlled) tWC Address OE tAS CS *2 tCW tAW tWP WE tDW Din Dout High impedance *1 tWR tDH Valid Data Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. Dout is the same phase of write data of this write cycle, if tWR is long enough. 12 HM6289 Series Write Timing Waveform (5) (OE = Low, WE = Controlled) tWC Address tCW CS tAW tAS WE tWHZ *2 Dout High impedance tDW Din Valid Data tDH *4 tWP *1 tWR tOH tOW *3 Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. If CS is low during this period, I/O pins are in the output state after tOW. Then the data input signals of opposite phase to the outputs must not be applied to them. 13 HM6289 Series Write Timing Waveform (6) (OE = Low, CS = Controlled) tWC Address tAS CS tAW tWP WE tCLZ Dout tWHZ *2 *1 tCW tWR High impedance tDW tDH Din Valid Data Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high impedance state. 14 HM6289 Series Low VCC Data Retention Characteristics (Ta = 0 to +70C) These characteristics are guaranteed for the L-version only. Parameter VCC for data retention Symbol VDR Min 2 Typ -- Max -- Unit V Test Conditions CS V CC - 0.2 V, Vin V CC - 0.2 V or 0 V Vin 0.2 V Data retention current I CCDR -- -- -- -- -- *1 50*2 35 -- -- *3 A A ns ns See retention waveform Chip deselect to data retention time Operation recovery time Notes: 1. t RC = Read cycle time 2. VCC = 3.0 V 3. VCC = 2.0 V t CDR tR 0 t RC -- Low V CC Data Retention Waveform Data Retention Mode VCC 4.5V tCDR 2.2V VDR CS VCC - 0.2V CS 0V tR 15 HM6289 Series Package Dimension HM6289JP/LJP Series (CP-24D) 15.63 16.00 Max 24 13 7.62 0.13 8.64 0.13 Unit: mm 1 0.74 12 3.50 0.26 0.21 2.40 + 0.24 - 1.30 Max 0.43 0.10 1.27 0.10 0.80 +0.25 -0.17 6.76 - 0.16 + 0.35 16 |
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